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Lattice Semiconductor
GAL20XV10B-20LP
FPGAs (Field Programmable Gate Array)
GAL20XV10B-20LP
2-GAL20XV10B-20LP
SPLD GAL Family 10 Macro Cells 71.4MHz 5V 24-Pin PDIP
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GAL20XV10B-20LP Description
Tech Specifications
Mounting Style
Through Hole
Operating Temperature
0 C to + 75 C
Supply Current
90 mA
Delay Time
20 ns
Supply Voltage - Min
4.75 V
Minimum Operating Temperature
0 C
Number of Macrocells
10
Package / Case
PDIP-24
Operating Supply Voltage
4.75 V to 5.25 V
Packaging
Tube / Tray
Number of Product Terms per Macro
4
Maximum Operating Frequency
71.4 MHz
Maximum Operating Temperature
+ 75 C
Logic Family
GAL
Supply Voltage - Max
5.25 V
Factory Pack Quantity
15
GAL20XV10B-20LP Documents
Download datasheets GAL20XV10B-20LP
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