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Lattice Semiconductor_M4LV-128/64-18VI
Lattice Semiconductor_M4LV-128/64-18VI
Lattice Semiconductor

M4LV-128/64-18VI  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M4LV-128/64-18VI
2-M4LV-128/64-18VI
CPLD MACH 4 Family 5K Gates 128 Macro Cells 35.7MHz/45.5MHz 3.3V 100-Pin TQFP Tray
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M4LV-128/64-18VI Description

CPLD MACH 4 Family 5K Gates 128 Macro Cells 35.7MHz/45.5MHz 3.3V 100-Pin TQFP Tray

Tech Specifications

Mounting Style
SMD/SMT
Delay Time
18 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
- 40℃
Number of Macrocells
128
Package / Case
TQFP-100
Operating Supply Voltage
4.5 V to 5.5 V
Packaging
Tube
Number of Product Terms per Macro
20
Maximum Operating Frequency
111.1 MHz
Number of Programmable I/Os
64
Maximum Operating Temperature
+ 85℃
Supply Voltage - Max
3.6 V
Factory Pack Quantity
90

M4LV-128/64-18VI Documents

Download datasheets M4LV-128/64-18VI

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