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Lattice Semiconductor_M4LV-128N/64-10JC
Lattice Semiconductor_M4LV-128N/64-10JC
Lattice Semiconductor

M4LV-128N/64-10JC  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M4LV-128N/64-10JC
2-M4LV-128N/64-10JC
Lattice Semiconductor-M4LV-128N/64-10JC-datasheet-200666.pdf
Lattice Semiconductor-M4LV-128N/64-10JC-datasheets-200666.pdf
CPLD MACH 4 Family 5K Gates 128 Macro Cells 71.4MHz/95.2MHz 3.3V 84-Pin PLCC Tube
In Stock : 785

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    Description Tech Specifications Documents Shopping Guide

    Tech Specifications

    Operating Temperature
    0°C ~ 70°C (TA)
    Voltage Supply - Internal
    4.75V ~ 5.25V
    ECCN
    EAR99
    Number of I/O
    64
    Programmable Type
    In System Programmable
    Mounting Type
    Surface Mount
    Product Status
    Active
    Supplier Device Package
    84-PLCC (29.29x29.29)
    Number of Macrocells
    128
    Series
    Mach® 4
    Package / Case
    84-LCC (J-Lead)
    REACH Status
    Vendor Undefined
    Mfr
    Lattice Semiconductor Corporation
    Delay Time tpd(1) Max
    7.5 ns
    HTSUS
    8542.39.0001
    Package
    Bulk
    RoHS Status
    RoHS non-compliant
    Moisture Sensitivity Level (MSL)
    3 (168 Hours)

    M4LV-128N/64-10JC Documents

    Download datasheets M4LV-128N/64-10JC

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