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Lattice Semiconductor_M4LV-192/96-7VC
Lattice Semiconductor_M4LV-192/96-7VC
Lattice Semiconductor

M4LV-192/96-7VC  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M4LV-192/96-7VC
2-M4LV-192/96-7VC
CPLD MACH 4 Family 7.5K Gates 192 Macro Cells 90.9MHz/111.1MHz 3.3V 144-Pin TQFP Tray
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M4LV-192/96-7VC Description

CPLD MACH 4 Family 7.5K Gates 192 Macro Cells 90.9MHz/111.1MHz 3.3V 144-Pin TQFP Tray

Tech Specifications

Mounting Style
SMD/SMT
Delay Time
7.5 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
0 C
Number of Macrocells
192
Package / Case
TQFP-144
Operating Supply Voltage
4.75 V to 5.25 V
Packaging
Tube
Number of Product Terms per Macro
20
Maximum Operating Frequency
111.1 MHz
Number of Programmable I/Os
96
Maximum Operating Temperature
+ 70 C
Supply Voltage - Max
3.6 V
Factory Pack Quantity
60

M4LV-192/96-7VC Documents

Download datasheets M4LV-192/96-7VC

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