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Lattice Semiconductor_M5LV-128/68-7VI
Lattice Semiconductor_M5LV-128/68-7VI
Lattice Semiconductor

M5LV-128/68-7VI  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M5LV-128/68-7VI
2-M5LV-128/68-7VI
Lattice Semiconductor-M5LV-128/68-7VI-datasheet-201041.pdf
Lattice Semiconductor-M5LV-128/68-7VI-datasheets-201041.pdf
CPLD MACH 5 Family 5K Gates 128 Macro Cells 83.3MHz/125MHz 3.3V 100-Pin TQFP Tray
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Description Tech Specifications Documents Shopping Guide

Tech Specifications

Operating Temperature
-40°C ~ 85°C (TA)
Voltage Supply - Internal
3V ~ 3.6V
ECCN
EAR99
Number of I/O
68
Programmable Type
In System Programmable
Mounting Type
Surface Mount
Product Status
Obsolete
Supplier Device Package
100-TQFP (14x14)
Number of Macrocells
128
Series
MACH® 5
Package / Case
100-LQFP
REACH Status
REACH Unaffected
Mfr
Lattice Semiconductor Corporation
Delay Time tpd(1) Max
7.5 ns
HTSUS
8542.39.0001
Package
Tray
RoHS Status
RoHS non-compliant
Base Product Number
M5LV-128
Moisture Sensitivity Level (MSL)
3 (168 Hours)

M5LV-128/68-7VI Documents

Download datasheets M5LV-128/68-7VI

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