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Lattice Semiconductor
M5LV-320/120-12YI
FPGAs (Field Programmable Gate Array)
M5LV-320/120-12YI
2-M5LV-320/120-12YI
CPLD MACH 5 Family 12.5K Gates 320 Macro Cells 52.6MHz/83.3MHz 3.3V 160-Pin PQFP Tray
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Tech Specifications
Mounting Style
SMD/SMT
Delay Time
12 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
- 40℃
Number of Macrocells
320
Package / Case
PQFP-160
Operating Supply Voltage
3.3 V
Packaging
Tray
Number of Product Terms per Macro
32
Maximum Operating Frequency
71.4 MHz
Number of Programmable I/Os
208
Maximum Operating Temperature
+ 85℃
Supply Voltage - Max
3.6 V
Factory Pack Quantity
120
M5LV-320/120-12YI Documents
Download datasheets M5LV-320/120-12YI
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