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Lattice Semiconductor_M5LV-384/120-7YI
Lattice Semiconductor_M5LV-384/120-7YI
Lattice Semiconductor

M5LV-384/120-7YI  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M5LV-384/120-7YI
2-M5LV-384/120-7YI
CPLD MACH 5 Family 15K Gates 384 Macro Cells 83.3MHz/125MHz 3.3V 160-Pin PQFP Tray
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Description Tech Specifications Documents Shopping Guide

M5LV-384/120-7YI Description

CPLD MACH 5 Family 15K Gates 384 Macro Cells 83.3MHz/125MHz 3.3V 160-Pin PQFP Tray

Tech Specifications

Mounting Style
SMD/SMT
Delay Time
7.5 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
- 40℃
Number of Macrocells
384
Package / Case
PQFP-160
Operating Supply Voltage
3.3 V
Packaging
Tray
Number of Product Terms per Macro
32
Maximum Operating Frequency
100 MHz
Number of Programmable I/Os
48
Maximum Operating Temperature
+ 85℃
Supply Voltage - Max
3.6 V
Factory Pack Quantity
120

M5LV-384/120-7YI Documents

Download datasheets M5LV-384/120-7YI

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