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Lattice Semiconductor_M5LV-512/160-20YI
Lattice Semiconductor_M5LV-512/160-20YI
Lattice Semiconductor

M5LV-512/160-20YI  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M5LV-512/160-20YI
2-M5LV-512/160-20YI
CPLD MACH 5 Family 20K Gates 512 Macro Cells 38.5MHz/50MHz 3.3V 208-Pin PQFP Tray
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M5LV-512/160-20YI Description

CPLD MACH 5 Family 20K Gates 512 Macro Cells 38.5MHz/50MHz 3.3V 208-Pin PQFP Tray

Tech Specifications

Mounting Style
SMD/SMT
Delay Time
20 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
- 40℃
Number of Macrocells
512
Package / Case
PQFP-208
Operating Supply Voltage
3.3 V
Packaging
Tray
Number of Product Terms per Macro
32
Maximum Operating Frequency
45.5 MHz
Number of Programmable I/Os
208
Maximum Operating Temperature
+ 85℃
Supply Voltage - Max
3.6 V
Factory Pack Quantity
120

M5LV-512/160-20YI Documents

Download datasheets M5LV-512/160-20YI

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