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ADTL084ARZ
FPGAs (Field Programmable Gate Array)
ADTL084ARZ
2-ADTL084ARZ
4 Channels 27mA per Channel 2pA 80 dB Instrumentational OP Amps 0.005μA 8V~36V ±4V~18V ADTL084 14 Pins 14-SOIC (0.154, 3.90mm Width)
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ADTL084ARZ Description
J-FET Amplifier 4 Circuit 14-SOIC
Tech Specifications
Low-Bias
YES
Unity Gain BW-Nom
5000 kHz
Dual Supply Voltage
15V
Average Bias Current-Max (IIB)
0.005μA
Surface Mount
YES
Current - Input Bias
2pA
Number of Functions
4
Package / Case
14-SOIC (0.154, 3.90mm Width)
Number of Channels
4
Lifecycle Status
PRODUCTION (Last Updated: 2 weeks ago)
Terminal Form
GULL WING
Number of Pins
14
Amplifier Type
J-FET
Input Offset Voltage (Vos)
5.5mV
Moisture Sensitivity Level (MSL)
1 (Unlimited)
Operating Temperature
-40°C~125°C
Neg Supply Voltage-Max (Vsup)
-18V
Neg Supply Voltage-Nom (Vsup)
-15V
Architecture
VOLTAGE-FEEDBACK
Mounting Type
Surface Mount
Pin Count
14
Power Supply Rejection Ratio (PSRR)
86dB
Input Offset Current-Max (IIO)
0.005μA
Packaging
Tube
Quiescent Current
1.2mA
Voltage - Supply, Single/Dual (±)
8V~36V ±4V~18V
Supply Voltage Limit-Max
18V
Terminal Pitch
1.27mm
Bias Current-Max (IIB) @25C
0.0001μA
Voltage Gain
106.02dB
Frequency Compensation
YES
Terminal Position
DUAL
Operating Supply Current
4.8mA
Low-Offset
NO
Bandwidth
5MHz
Number of Terminations
14
Input Voltage Noise Density
16nV/sqrt Hz
Supply Voltage
15V
Height
1.5mm
ECCN Code
EAR99
Width
4mm
Lead Free
Contains Lead
Qualification Status
Not Qualified
Pbfree Code
no
RoHS Status
ROHS3 Compliant
Common Mode Rejection Ratio
80 dB
REACH SVHC
No SVHC
Slew Rate
20V/μs
JESD-609 Code
e3
Factory Lead Time
8 Weeks
Voltage - Input Offset
1.5mV
Time@Peak Reflow Temperature-Max (s)
30
Peak Reflow Temperature (Cel)
260
Length
8.75mm
Contact Plating
Tin
Output Current per Channel
27mA
Part Status
Active
Base Part Number
ADTL084
ADTL084ARZ Documents
Download datasheets ADTL084ARZ
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