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Lattice Semiconductor
M4LV-256/128-18YI
FPGAs (Field Programmable Gate Array)
M4LV-256/128-18YI
2-M4LV-256/128-18YI
CPLD MACH 4 Family 10K Gates 256 Macro Cells 35.7MHz/45.5MHz 3.3V 208-Pin PQFP Tray
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M4LV-256/128-18YI Description
CPLD MACH 4 Family 10K Gates 256 Macro Cells 35.7MHz/45.5MHz 3.3V 208-Pin PQFP Tray
Tech Specifications
Mounting Style
SMD/SMT
Delay Time
18 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
- 40℃
Number of Macrocells
256
Package / Case
PQFP-208
Operating Supply Voltage
4.5 V to 5.5 V
Packaging
Tube
Number of Product Terms per Macro
20
Maximum Operating Frequency
111.1 MHz
Number of Programmable I/Os
128
Maximum Operating Temperature
+ 85℃
Supply Voltage - Max
3.6 V
Factory Pack Quantity
24
M4LV-256/128-18YI Documents
Download datasheets M4LV-256/128-18YI
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