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Lattice Semiconductor_M4LV-64/32-18VI48
Lattice Semiconductor_M4LV-64/32-18VI48
Lattice Semiconductor

M4LV-64/32-18VI48  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M4LV-64/32-18VI48
2-M4LV-64/32-18VI48
CPLD MACH 4 Family 2.5K Gates 64 Macro Cells 35.7MHz/45.5MHz 3.3V 48-Pin TQFP Tray
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Description Tech Specifications Documents Shopping Guide

M4LV-64/32-18VI48 Description

CPLD MACH 4 Family 2.5K Gates 64 Macro Cells 35.7MHz/45.5MHz 3.3V 48-Pin TQFP Tray

Tech Specifications

Mounting Style
SMD/SMT
Delay Time
18 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
- 40℃
Number of Macrocells
64
Package / Case
TQFP-48
Operating Supply Voltage
4.5 V to 5.5 V
Packaging
Tube
Number of Product Terms per Macro
20
Maximum Operating Frequency
111.1 MHz
Number of Programmable I/Os
32
Maximum Operating Temperature
+ 85℃
Supply Voltage - Max
3.6 V
Factory Pack Quantity
250

M4LV-64/32-18VI48 Documents

Download datasheets M4LV-64/32-18VI48

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