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Lattice Semiconductor
M4LV-96/48-12VC
FPGAs (Field Programmable Gate Array)
M4LV-96/48-12VC
2-M4LV-96/48-12VC
CPLD MACH 4 Family 3.75K Gates 96 Macro Cells 58.8MHz/76.9MHz 3.3V 100-Pin TQFP Tray
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M4LV-96/48-12VC Description
CPLD MACH 4 Family 3.75K Gates 96 Macro Cells 58.8MHz/76.9MHz 3.3V 100-Pin TQFP Tray
Tech Specifications
Mounting Style
SMD/SMT
Delay Time
12 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
0 C
Number of Macrocells
96
Package / Case
TQFP-100
Operating Supply Voltage
4.75 V to 5.25 V
Packaging
Tube
Number of Product Terms per Macro
20
Maximum Operating Frequency
111.1 MHz
Number of Programmable I/Os
48
Maximum Operating Temperature
+ 70 C
Supply Voltage - Max
3.6 V
Factory Pack Quantity
90
M4LV-96/48-12VC Documents
Download datasheets M4LV-96/48-12VC
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