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Lattice Semiconductor
M5LV-320/120-7YC
FPGAs (Field Programmable Gate Array)
M5LV-320/120-7YC
2-M5LV-320/120-7YC
CPLD MACH 5 Family 12.5K Gates 320 Macro Cells 83.3MHz/125MHz 3.3V 160-Pin PQFP Tray
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M5LV-320/120-7YC Description
CPLD MACH 5 Family 12.5K Gates 320 Macro Cells 83.3MHz/125MHz 3.3V 160-Pin PQFP Tray
Tech Specifications
Mounting Style
SMD/SMT
Delay Time
7.5 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
0 C
Number of Macrocells
320
Package / Case
PQFP-160
Operating Supply Voltage
3.3 V
Packaging
Tray
Number of Product Terms per Macro
32
Maximum Operating Frequency
100 MHz
Number of Programmable I/Os
256
Maximum Operating Temperature
+ 70 C
Supply Voltage - Max
3.6 V
Factory Pack Quantity
120
M5LV-320/120-7YC Documents
Download datasheets M5LV-320/120-7YC
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